View CY14B104L-BV45XIT_2481288.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-mbit (512k x 8/256k x 16) nvsram preliminary cy14b104l/cy14b104n cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07102 rev. *e revised june 29, 2007 feature ? 15 ns, 25 ns, and 45 ns access times ? internally organized as 512k x 8 or 256k x 16 ? hands-off automatic store on power down with only a small capacitor ? store to quantumtrap ? nonvolatile elements is initiated by software, device pin or autostore ? on power down ? recall to sram initiated by software or power up ? infinite read, write, and recall cycles ? 8 ma typical i cc at 200 ns cycle time ? 200,000 store cycles to quantumtrap ? 20 year data retention ? single 3v +20%, C10% operation ? commercial and industrial temperatures ? fbga and tsop - ii packages ? rohs compliance functional description the cypress cy14b104l/cy14b104n is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 512k words of 8 bits each or 256k wo rds of 16 bits each. the embedded nonvolatile elements incorp orate quantumtrap technology producing the worlds most r eliable nonvolatile memory. the sram provides infinite read and write cycles, while independent, nonvolatile data r esides in the highly reliable quantumtrap cell. data transfers fr om the sram to the nonvolatile elements (the store operation ) takes place automatically at power down. on power u p, data is restored to the sram (the recall operation) from t he nonvolatile memory. both the store and recall operations are also available under software contro l. logic block diagram a 0 - a 18 address we oe ce v cc v ss v cap dq0 - dq15 hsb cy14b104l/cy14b104n bhe ble [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 2 of 21 pin configurations we v cc a 11 a 10 v cap a 6 a 0 a 3 ce dq10 dq8 dq9 a 4 a 5 dq13 dq12 dq14 dq15 v ss a 9 a 8 oe v ss a 7 dq0 bhe nc a 17 a 2 a 1 ble v cc dq2 dq1 dq3 dq4 dq5 dq6 dq7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a cf g h a 16 nc nc dq11 48 - fbga top view (not to scale) (x16) nc a 8 nc nc v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 17 a 18 nc 1 2 34 5 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 nc we dq7 hsb nc v ss v cc v cap nc (x8) v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 ble a 9 ce a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 11 a 10 a 14 bhe oe a 15 a 16 a 17 1 23 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) we dq7 a 0 v ss v cc dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 v cap (x16) [1] [1] note 1. expandable to 8mbit,16mbit [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 3 of 21 pin definitions pin name io type description a 0 C a 16 input address inputs used to select one of the 131,072 by tes of the nvsram . dq0 C dq7 input output bidirectional data io lines . used as input or output lines depending on operat ion. we input write enable input, active low . when selected low, enables data on the io pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. io pins are tri-stated on deasserting oe high. v ss ground ground for the device. must be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input output hardware store busy (hsb) . when low this output indicates a hardware store i s in progress. when pulled low external to the chip it initiates a nonv olatile store operation. a weak internal pull up resistor keeps this pin high if not connected. (con nection optional) v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . do not connect this pin to the die. pin configurations (continued) a 17 dq7 dq6 dq5 dq4 v cc dq3 dq2 dq1 dq0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 23 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54 - tsop ii top view (not to scale) oe ce v cc nc v ss nc a 9 nc nc nc nc nc nc 54 53 52 51 49 50 hsb bhe ble dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 (x16) [1] [1] [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 4 of 21 device operation the cy14b104l/cy14b104n nvsram is made up of two functional components paired in the same physical c ell. they are an sram memory cell and a nonvolatile quantumtr ap cell. the sram memory cell operates as a standard f ast static ram. data in the sram can be transferred to the non volatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architectu re allows all cells to be stored and recalled in paral lel.during the store and recall operations sram read and write operations are inhibited. the cy14b104l/cy14b104n suports infinite reads and writes just like a typic al sram.in addition,it provides infinite recall operations fro m the nonvolatile cells and up to 200k store operations. sram read the cy14b104l/cy14b104n performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0-18 /a 0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each will be accessed. when the read is initiated by an addre ss transition, the outputs will be valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and will remain valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior t o entering the write cycle and must remain stable unt il either ce or we goes high at the end of the cycle. the data on the common io pins dq 0C15 will be written into the memory if the data is valid t sd before the end of a we controlled write or before the end of an ce controlled write. it is recommended that oe kept high during the entire write cycle to avoid d ata bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104l/cy14b104n stores data to nvsram using one of the three storage operations. these three op erations are hardware store activated by hsb , software store activated by an address sequence, and autostore on device power down. autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b104l/cy14b104n. during normal operation, the device draws current f rom v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation will be initiated with power provid ed by the v cap capacitor. figure 1 shows the proper connection of the storage capacito r (v cap ) for automatic store operation. refer to the dc electrical characteristics on page 8 for the size of v cap . to reduce unnecessary nonvolatile stores, autostore , and hardware store operations will be ignored unless at least one write operation has taken place since the most recen t store or recall cycle. software initiated store cycles are performed regardless of whether a write operati on has taken place. monitor the hsb signal by the system to detect if an autostore cycle is in progress. figure 1. autostore mode hardware store operation the cy14b104l/cy14b104n provides the hsb pin for controlling and acknowledging the store operations. u se the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b104l/cy14b104n condi- tionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram took pla ce since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven l ow to indicate a busy condition while the store (initiated by any me ans) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. aft er hsb goes low, the cy14b104l/cy14b104n continues sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the cy14b104l/cy14b104n continues to drive the hsb pin low, releasing it only when the store is compl ete. v cc v cc v cap v cap we 10k ohm 0.1 f u v cc v cc v cap v cap 0.1 f u [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 5 of 21 upon completion of the store operation the cy14b104l/cy14b104n remains disabled until the hsb pin returns high. leave the hsb unconnected if is not used. hardware recall (power up) during power up or after any low power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and takes t hrecall to complete. software store transfer data from the sram to the nonvolatile memo ry with a software address sequence. the cy14b104l/cy14b104n software store cycle is initiated by executing sequ ential ce -controlled read cycles from six specific address l ocations in exact order. during the store cycle an erase of the previous nonvolatile data is first performed, follo wed by a program of the nonvolatile elements. once a store cy cle is initiated, further input and output are disabled un til the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence. if the re are intervening read or write accesses, the sequence wi ll be aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with ce controlled reads or oe controlled reads. once the sixth address in the sequence has been entered, the store cycle commences and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, althou gh it is not necessary that oe be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall transfer the data from the nonvolatile memory to th e sram by a software address sequence. a software recall c ycle is initiated with a sequence of read operations in a m anner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle internally, recall is a two-step procedure. first, t he sram data is cleared and second, the nonvolatile informa tion is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 6 of 21 preventing autostore the autostore function can be disabled by initiatin g an autostore disable sequence. a sequence of read oper ations is performed in a manner similar to the software sto re initiation. to initiate the autostore disable seque nce, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore can be re-enabled by initiating an au tostore enable sequence. a sequence of read operations is p erformed in a manner similar to the software recall initiatio n. to initiate the autostore enable sequence, the followi ng sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power d own cycles. the part comes from the factory with autost ore enabled. table 1. mode selection ce we oe a15 - a0 mode io power h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [2,3,4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [2,3,4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [2,3,4] notes 2. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a non volatile cycle. 3. while there are 19 address lines on the cy14b104l /cy14b104n, only the lower 16 lines are used to con trol software modes. 4. io state depends on the state of oe . the io table shown assumes oe low. [2,3,4] [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 7 of 21 data protection the cy14b104l/cy14b104n protects data from corrupti on during low-voltage conditions by inhibiting all ext ernally initiated store and write operations. the low volta ge condition is detected when v cc < v switch . if the cy14b104l/cy14b104n is in a write mode (both ce and we low) at power up, after a recall, or after a store, t he write will be inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations refer cy application note an1064. [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 8 of 21 maximum ratings exceeding the maximum ratings may impair the useful life of the device. storage temperature ............................... .. C65 c to +150 c ambient temperature with power applied...................................... ....... C55 c to +150 c supply voltage on v cc relative to gnd ......... C0.5v to 4.1v voltage applied to outputs in high-z state .................................... ...C0.5v to v cc + 0.5v input voltage ...................................... ...... C0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential ..................C2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ........................................... ........ 1.0w surface mount pb soldering temperature (3 seconds)............................. ............. +260 c output short circuit current [5] .................................... 15 ma static discharge voltage........................... ............... > 2001v (per mil-std-883, method 3015) latch-up current ................................... ................ > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial C40 c to +85 c 2.7v to 3.6v above table contains advanced information. dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) parameter description test conditions min max unit i cc1 average v cc current t avav = 15 ns t avav = 25 ns t avav = 45 ns dependent on output loading and cycle rate.values obtained without output loads. i out = 0 ma commercial 70 65 50 ma ma ma industrial 75 70 52 ma ma ma i cc2 average v cc current during store all inputs dont care, v cc = max average current for duration t store 3 ma i cc3 average v cc current at t avav = 200 ns, 3v, 25c typical we > (v cc C 0.2). all other i/p cycling. dependent on output loading and cycle rate. values obtained without output loads. 25 ma i cc4 average v cap current during autostore cycle all inputs dont care, v cc = max average current for duration t store 3 ma i sb v cc standby current ce > (v cc C 0.2). all others v in < 0.2v or > (v cc C 0.2v). standby current level after nonvolatile cycle is co mplete. inputs are static. f = 0 mhz. 1 ma i ix input leakage current v cc = max, v ss < v in < v cc C1 +1 a i oz off-state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih C1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v cc C 0.5 0.8 v v oh output high voltage i out = C2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 35 57 f capacitance [7] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7 pf c out output capacitance 7 pf notes 5. outputs shorted for no more than one second. no m ore than one output shorted at a time. 6. typical conditions for the active current shown o n the front page of the data sheet are average valu es at 25c (room temperature), and v cc = 3v. not 100% tested. 7. these parameters are guaranteed but not tested. [6] [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 9 of 21 thermal resistance parameter description test conditions 48-fbga 44-tsop ii 5 4-tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. tbd tbd tbd c/w jc thermal resistance (junction to case) tbd tbd tbd c/w ac test loads 3.0v output 5 pf r1 577 r2 789 3.0v output 30 pf r1 577 r2 789 for tri-state specs [7] [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 10 of 21 ac test conditions input pulse levels ................................. .................. 0v to 3v input rise and fall times (10% - 90%) .............. ......... <5 ns input and output timing reference levels ........... .........1.5v notes 8. we must be high during sram read cycles. 9. device is continuously selected with ce and oe both low. 10. measured 200 mv from steady state output voltag e. 11. if we is low when ce goes low, the outputs remain in the high impedance state. ac switching characteristics parameters description 15ns 25ns 45ns unit cypress parameters alt. parameters min max min max min. max. sram read cycle t ace t acs chip enable access time 15 25 45 ns t rc [8] t rc read cycle time 15 25 45 ns t aa [9] t aa address access time 15 25 45 ns t doe t oe output enable to data valid 10 12 20 ns t oha t oh output hold after address change 3 3 3 ns t lzce [10] t lz chip enable to output active 3 3 3 ns t hzce [10] t hz chip disable to output inactive 7 10 15 ns t lzoe [10] t olz output enable to output active 0 0 0 ns t hzoe [10] t ohz output disable to output inactive 7 10 15 ns t pu [7] t pa chip enable to power active 0 0 0 ns t pd [7] t ps chip disable to power standby 15 25 45 ns t dbe - byte enale to data valid 10 12 22 ns t lzbe - byte enable to output active 0 0 0 ns t hzbe - byte disable to output inactive 7 10 22 ns sram write cycle t wc t wc write cycle time 15 25 45 ns t pwe t wp write pulse width 10 20 30 ns t sce t cw chip enable to end of write 15 20 30 ns t sd t dw data setup to end of write 5 10 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 15 20 30 ns t sa t as address setup to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [10,11] t wz write enable to output disable 7 10 15 ns t lzwe [10] t ow output active after end of write 3 3 3 ns t bw - byte enable to end of write 15 20 30 ns [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 11 of 21 autostore/power up recall parameters description cy14b104l/cy14b104n unit min max t hrecall [12] power up recall duration 20 ms t store [13] store cycle duration 15 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s software controlled store/recall cycle [14,15] parameters description 15ns 25ns 45ns unit min max min max min. max. t rc store/recall initiation cycle time 15 25 45 ns t as address setup time 0 0 0 ns t cw clock pulse width 12 20 30 ns t ghax address hold time 1 1 1 ns t recall recall duration 100 100 100 s t ss [16,17] soft sequence processing time 70 70 70 s notes 12. t hrecall starts from the time v cc rises above v switch. 13. if an sram write has not taken place since the l ast nonvolatile cycle, no store will take place. 14. the software sequence is clocked with ce controlled or oe controlled reads. 15. the six consecutive addresses must be read in th e order listed in the mode selection table. we must be high during all six consecutive cycles. 16. this is the amount of time it takes to take acti on on a soft sequence command. v cc power must remain high to effectively register com mand. 17. commands such as store and recall lock out io un til operation is complete which further increases t his time. see specific command. 18. read and write cycles in progress before hsb are supplied this amount of time to complete. hardware store cycle parameters description cy14b104l/cy14b104n unit min max t delay [18] time allowed to complete sram cycle 1 70 s t hlhx hardware store pulse width 15 ns switching waveforms figure 2. sram read cycle #1: address controlled [8,9,19] t rc t aa t oha address dq (data out) data valid [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 12 of 21 figure 3. sram read cycle #2: ce and oe controlled [8,19,21] figure 4. sram write cycle #1: we controlled [19,20,21] switching waveforms (continued) address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe data valid active standby t pu dq (data out) icc t lzbe t dbe t hzbe hzoe t t hzce bhe , ble t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data bhe , ble t bw [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 13 of 21 figure 5. sram write cycle #2: ce controlled [21] figure 6. autostore/power up recall switching waveforms (continued) t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid bhe , ble t bw v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 14 of 21 figure 7. ce -controlled software store/recall cycle [15] figure 8. oe -controlled software store/recall cycle [15] switching waveforms (continued) a a t rc t rc t as t cw t glax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a a a t rc t rc t sa t sce t ghax t store / t recall data valid data valid address # 1 address # 6 high impedance address ce oe dq (data) a a a a a a a a a a a a t rc t rc address # 1 address # 6 address t as t cw t ghax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 15 of 21 figure 9. hardware store cycle [18] figure 10. soft sequence processing [16,17] switching waveforms (continued) t ss t ss [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 16 of 21 notes 19. hsb must remain high during read and write cycles. 20. ce or we must be > v ih during address transitions. 21. bhe and ble are applicable for x16 configuration only. ordering information speed (ns) ordering code package diagram package type operating range 15 cy14b104l-zs15xct 51-85087 44-pin tsop ii commercial cy14b104l-zs15xit 51-85087 44-pin tsop ii industrial cy14b104l-zs15xi 51-85087 44-pin tsop ii cy14b104l-zsp15xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp15xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp15xi 51-85160 54-pin tsop ii cy14b104n-ba15xct 51-85128 48-ball fbga commercial cy14b104n-ba15xit 51-85128 48-ball fbga industrial cy14b104n-ba15xi 51-85128 48-ball fbga cy14b104n-zs15xct 51-85087 44-pin tsop ii commercial cy14b104n-zs15xit 51-85087 44-pin tsop ii industrial cy14b104n-zs15xi 51-85087 44-pin tsop ii cy14b104n-zsp15xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp15xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp15xi 51-85160 54-pin tsop ii 25 cy14b104l-zs25xct 51-85087 44-pin tsop ii commercial cy14b104l-zs25xit 51-85087 44-pin tsop ii industrial cy14b104l-zs25xi 51-85087 44-pin tsop ii cy14b104l-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp25xi 51-85160 54-pin tsop ii cy14b104n-ba25xct 51-85128 48-ball fbga commercial cy14b104n-ba25xit 51-85128 48-ball fbga industrial cy14b104n-ba25xi 51-85128 48-ball fbga cy14b104n-zs25xct 51-85087 44-pin tsop ii commercial cy14b104n-zs25xit 51-85087 44-pin tsop ii industrial cy14b104n-zs25xi 51-85087 44-pin tsop ii cy14b104n-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp25xi 51-85160 54-pin tsop ii [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 17 of 21 45 cy14b104l-bv45xct 51-85128 48-ball fbga commercial CY14B104L-BV45XIT 51-85128 48-ball fbga industrial cy14b104l-bv45xi 51-85128 48-ball fbga cy14b104l-zs45xct 51-85087 44-pin tsop ii commercial cy14b104l-zs45xit 51-85087 44-pin tsop ii industrial cy14b104l-zs45xi 51-85087 44-pin tsop ii cy14b104l-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp45xi 51-85160 54-pin tsop ii cy14b104n-bv45xct 51-85128 48-ball fbga commercial cy14b104n-bv45xit 51-85128 48-ball fbga industrial cy14b104n-bv45xi 51-85128 48-ball fbga cy14b104n-zs45xct 51-85087 44-pin tsop ii commercial cy14b104n-zs45xit 51-85087 44-pin tsop ii industrial cy14b104n-zs45xi 51-85087 44-pin tsop ii cy14b104n-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp45xi 51-85160 54-pin tsop ii ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 18 of 21 option: t - tape & reel blank - std. speed: 15 - 15 ns 25 - 25 ns data bus: l - x8 n - x16 density: 104 - 4 mb voltage: b - 3.0v cypress part numbering nomenclature cy 14 b 104 l - zs p 15 x c t nvsram 14 - autostore + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (C40 to 85c) pb-free package: ba - 48 fbga zs - tsop ii p - 54 pin blank - 44 pin 45 - 45 ns [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 19 of 21 package diagrams figure 11. 54-pin tsop ii (51-85160) figure 12. 44-pin tsop ii (51-85087) 51-85160-** maxmin. 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 20 of 21 ? cypress semiconductor corporation, 2007. the info rmation contained herein is subject to change witho ut notice. cypress semiconductor corporation assume s no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any l icense under patent or other rights. cypress produc ts are not warranted nor intended to be used for medical, life support, life saving, critic al control or safety applications, unless pursuant to an express written agreement with cypress. furth ermore, cypress does not authorize its products for use as critical components in life-sup port systems where a malfunction or failure may rea sonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implie s that the manufacturer assumes all risk of such us e and in doing so indemnifies cypress against all c harges. figure 13. 48-ball fbga (6 mm x 10 mm x 1.2 mm) autostore and quantumtrap are registered trademarks of simtek corporation. all products and company names mention ed in this document are the trademarks of their respectiv e holders. package diagrams (continued) a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 bc d e fg h 6 5 4 6 5 2 3 1 dh fg e c b a 6.000.10 10.000.10 a 10.000.10 6.000.10 b 1.875 2.625 0.36 51-85128-*d [+] feedback [+] feedback
cy14b104l/cy14b104n preliminary document #: 001-07102 rev. *e page 21 of 21 document history page document title: cy14b104l/cy14b104n 1-mbit (128k x 8) nvsram document number: 001-07102 rev. ecn no. issue date orig. of change description of change ** 431039 see ecn tup new data sheet *a 489096 see ecn tup removed 48 ssop package added 48 fbga and 54 tsopii packages updated part numbering nomenclature and ordering inf ormation added soft sequence processing time waveform *b 499597 see ecn pci removed 35 ns speed bin added 55 ns speed bin. updated ac table for the sam e changed unlimited read/write to infinite read/w rite features section: changed typical i cc at 200-ns cycle time to 8 ma changed store cycles from 500k to 200k cycles shaded commercial grade in operating range table modified icc/isb specs 48 fbga package nomenclature changed from bw to bv modified part nomenclature table. changes reflected in the ordering infor- mation table *c 517793 see ecn tup removed 55ns speed bin changed pinout for 44tsopii and 54tsopii packages changed i sb to 1ma changed i cc4 to 3ma changed v cap min to 35 f changed v ih max to vcc + 0.5v changed t store to 15ms changed t pwe to 10ns changed t sce to 15ns changed t sd to 5ns changed t aw to 10ns removed t hlbl added timing parameters for bhe and ble - t dbe , t lzbe , t hzbe , t bw removed min specification for vswitch changed t glax to 1ns added t delay max of 70us changed t ss specification from 70us min to 70us max *d 774001 see ecn uha changed the datasheet from advanc e information to preliminary 48 fbga package code changed from bv to ba removed 48 fbga package in x8 configuration in orderi ng information. changed t dbe to 10ns in 15ns part changed t hzbe in 15ns part to 7ns and in 25ns part to10ns changed t bw in 15ns part to 15ns and in 25ns part to 20ns changed t glax to t ghax changed the value of i cc3 to 25ma changed the value of t aw in 15ns part to15ns changed a 18 and a 19 pins in fbga pin configuration to nc *e 914220 see ecn uha included all the information for 45ns part in this datasheet [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY14B104L-BV45XIT

	To Download CY14B104L-BV45XIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .